1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly to an ion repulsion structure having a plurality of wells in a semiconductor substrate and multi-level metallic layers surrounding fuse windows.
2. Description of Related Art
In semiconductor devices, an electrical test is performed on each semiconductor chip after the wafer-state in which active or passive elements are formed on a semiconductor substrate, and before packaging of the chip. In this test, a probe is brought into contact with bonding is pad of the semiconductor chip so that its performance can be tested.
However, the current trend towards the integration of semiconductor devices allows the shortening of the distance between lines, tending to increase the number of defects tends arising in the manufacturing process, thereby reducing yields. Therefore, integrated circuits (ICs), for example semiconductor memories such as static random access memory (SRAM) or dynamic random access memory (DRAM), are each provided with a redundancy circuit for repairing defects present in some memory cells which arose in the memory manufacturing process. For example, defective cells may be replaced by the redundancy circuit by cutting fuses associated with the defective cells on the basis of the test results, and then activating a spare row or column of cells. Typical methods for cutting a fuse are using a laser beam to melt the fuse or passing a high current through the fuse.
As an example, a semiconductor device provided with a fuse according to the prior art method will be described briefly. A cross sectional view of a portion of a semiconductor device is illustrated schematically in FIG. 1.
As shown in FIG. 1, a substrate 100 having a main surface includes a fuse forming area 200, a bonding pad forming area 300, and a semiconductor element forming area 400.
First, the semiconductor substrate 100, which is, for example, a silicon, germanium or gallium-arsenide substrate, is provided. Moreover, the substrate can be an epitaxial layer or silicon on insulator (SOI) layer. For simplicity, a P-type silicon substrate is utilized in the embodiment.
Over the semiconductor substrate 100, semiconductor elements are formed by a conventional method. For example, a thermal oxidation step, such as the LOCOS method, is carried out to form a field oxide layer 120 over the substrate 100, thereby defining an active region of the transistor and capacitor. Then steps such as deposition, micro-lithography, and ion implantation are carried out to form the elements in the active region of the semiconductor element forming area 400. The elements include upper and lower electrode plates, a polysilicon gate structure, an N-type source diffusion region and an N-type drain diffusion region. The gate structure can be a word line (not shown).
Next, an insulating layer or an inter-level dielectric layer 140(ILD) is formed over the field oxide 120 and the substrate 100 and then planarized by means of thermal reflow process. The insulating layer 140 may be made of silicon dioxide deposited by means of chemical vapor deposition. More specifically, the insulating layer 140 can be a silicon dioxide layer deposited by means of a low-pressure chemical vapor deposition (LPCVD) process by reacting tetra-ethyl-ortho-silicate (TEOS). Alternatively, the insulating layer 140 can be a borophosphosilicate glass layer (BPSG) deposited by means of an atmospheric-pressure chemical vapor deposition (APCVD) process by the reaction of TEOS and O.sub.3 /O.sub.2, with the addition of tri-ethyl-borate (TEB) and tri-methyl-phosphate (TMP). Preferably, the insulating layer 140 has a thickness of about 3000.about.10000 .ANG..
Furthermore, as the demand for higher integration increases, a multi-level interconnected structure becomes applicable to these ICs. The multi-level interconnected structure can provide the IC not only with a higher integration but also a freedom of design. For example, semiconductor elements, such as field effect transistors, capacitors, metal lines, etc., can be formed in the semiconductor elements forming area 400.
Still referring to FIG. 1, a lower metallic layer 420 composed of a single aluminum or aluminum alloy and an inter-metal dielectric (IMD) 160 made of low-permittivity insulating materials are sequentially deposited on the insulating layer 140. Aluminum wiring and low-permittivity insulating materials provide a large margin for improving RC delay. In addition, a lower dielectric constant also reduces the line capacitance and thus cuts down the cross talk between conductors. Next, a via hole is formed in the IMD 160 by means of a conventional photo-etch process. Then, a metal layer made of tungsten material is deposited in the via hole as well as on the IMD 160. Etching back the metal layer 300 leaves a via plug 440 in the via hole. After that, an upper metallic layer 460 composed of a single aluminum or aluminum alloy is formed. Electrical connections are made between the upper metallic layer 460 and the lower metallic layer 420 through the use of via plug 440.
A fuse is generally formed over field oxide layers and covered by more than two insulating layers in the fuse forming area 200. The fuse 210 is preferably composed of metal materials such as aluminum, a silicide such as tungsten silicide, polysilicon, or a polycide such as titanium polycide. For example, a polysilicon fuse 210 is formed simultaneously with other polysilicon conducting paths. It is arranged on the same layer together with other electronic components such as transistors, capacitors, bit lines and the like. Furthermore, it is sandwiched by the field oxide layer 120 and insulating layers such as the borophosphosilicate glass layer (BPSG), the inter-metal dielectric layer (IMD) 160 and so on, to prevent the shorting of the fuse to the substrate during a laser beam cutting process.
Next, in the bonding pad forming area 300, by means of a conventional photo-etching process, a bonding pad 320 may be formed simultaneously with the upper metallic layer 460.
Then, a silicon oxide layer 180, which constitutes a part of a final passivation layer, is formed over the insulating layer (IMD) 160, bonding pad 320, upper metallic layer 460 and the like, by a chemical vapor deposition (CVD) method to avoid damage due to any temperature rise.
Next, as shown in FIG. 2, by a conventional photo-etching process, an aperture (fuse window) 280 is formed above the fuse 210 and a hole 340 is formed to expose portions of the bonding pad 320. Then, a probe (not shown) is brought into contact with the surface of the bonding pad 320 through this hole 340 and an electrical test is conducted. When a defective memory cell is discovered as a result of this test, a laser beam is radiated to the fuse 210 through the insulating layers 140 and 160 located below the fuse window 280 in order to melt the fuse 210 and form a laser repair hole 210'. In this manner, the defective cells are replaced by the redundancy circuit and the corresponding spare row or column of cells is activated.
However, it is also very possible that moisture and contamination from the air might enter the exposed insulating 140 and 160 through the fuse window 280. Furthermore, after cutting the fuse 210 by the laser beam, mobile ions such as aluminum ions, sodium ions and potassium ions (Al.sup.+3, Na.sup.+, K.sup.+) are able to penetrate into the exposed portions of the insulating layers and diffuse to nearby semiconductor devices through the laser repair hole 210'. This means that the contaminants could cause the occurrence of corrosion, the failure of the highly accelerated stress test (HAST) described below in table 1, and the reduction of reliability and yields.
TABLE 1 Test name Highly Accelerated Stress Test Acronym HAST Test To evaluate the reliability of packaged devices purpose in humid environments. It employs unusual conditions of temperature, humidity, and bias which accelerate the penetration of electrolytic moisture through the external protective material. Test 130.degree. C.; 85% RH; Vcc = individual spec. value conditions Example Aluminum corrosion